1. Field of Invention
The present invention relates to a single or a plurality of digital systems operating synchronously with a single or a plurality of clock signals, a method for adjusting in timing the clock signals of such a digital system, and a recording medium having a processing program recorded on it, the processing program being executed in the adjusting method.
Particularly, the present invention is very effective in case that the number of digital circuit elements being components of a digital system or in case that the frequency of a clock signal is high.
2. Description of Related Art
A digital system is ordinarily composed of logic elements of three kinds which are an AND element, an OR element and a NOT element, and a memory element called a flip-flop to memorize either of the two states (1 bit) of true (logic value “1”) and false (logic value “0”).
The most basic flip-flop is composed of three terminals of one input terminal, one output terminal and a clock terminal, and has a function which copies a digital signal of the input terminal to the output terminal at rising of a digital signal called a clock signal applied to the clock terminal and holds this digital signal until rising of the next clock signal.
Generally, a digital system operating according to a finite number of clock signals is called a synchronous circuit, in which the time difference between clock signals reaching the clock terminals of the respective flip-flops has an influence upon operation of the whole system. Generally, a signal line to supply a clock signal to each flip-flop often has a buffer inserted in the course of it or adopts a special circuit contrived in physical wiring, which is called a clock circuit here.
For example, while a time difference of 1 ns is a difference of 1% in case of a clock frequency of 10 MHz, namely, in case of a clock cycle of 100 ns, the same time difference of 1 ns is a difference of 10% in case of a clock frequency of 100 MHz, namely, in case of a clock cycle of 10 ns and needs to be compensated. In short, the higher a clock frequency is, the more accurate a timing adjusting technique needs to be.
A conventional countermeasure to counter a clock timing error in a digital system includes such two ways as;    (1) a countermeasure technique in which a designer performs a manual adjustment so as to make a clock timing error as small as possible at the time of designing a digital system, and    (2) a countermeasure technique of providing an adjusting circuit compensating for a clock timing error in a clock circuit in a digital system.
However, countermeasure (1) cannot solve the following problems. That is to say, electronic circuit elements such as a transistor, a resistor and a capacitor vary respectively in characteristic, and variation of the respective elements is not apparent until a system is actually formed. This is a characteristic particularly remarkably appearing in elements in an integrated circuit. It is a clock timing that is most influenced by this variation, which determines the upper limit of the operating frequency of a digital synchronous system.
In such a way, since variation in these elements cannot be completely grasped at the time of design of a digital system, a technique has been taken which designs and manufactures it allowing a certain range of variation or which measures an actual degree of variation by repeating its trial manufacture. However, this technique has apparently a limit and has not been able to utilize the characteristic of each element to its limit.
As another problem, a manual adjustment has a limit in scale of a handleable circuit, and has not been able to adjust the whole of a large-scale digital system such as a computer system as a practical problem. And a technique of separating a large-scale problem into partial problems, the technique being a familiar method in handling a large-scale problem is not preferable due to limiting a range of adjustment.
A problem in countermeasure (2) is that although an adjusting circuit is inserted, with the increase of a circuit scale the adjusting and search space becomes more extensive and results in making it impossible to perform adjustment within a practical time. On the other hand, an adjusting circuit which can perform adjustment within a practical time can adjust only a small part of a digital system and its effect is extremely limited.
In case that the above-mentioned digital system is made as an integrated circuit, it is further characterized by the following two points.
The first point is that the interior of an integrated circuit cannot be modified and must be all determined at design. Thereupon, a technique of inserting an adjusting circuit is taken, but since the adjusting and search space becomes very extensive, it is impossible to perform adjustment in consideration of operation of the whole circuit. If a new technique of the present invention as described later is not used, it is impossible to perform a timing adjustment in consideration of operation of the whole circuit after the integrated circuit chip has been manufactured.
The second point is that elements in an integrated circuit chip are large in variation and variation in parameters (the values of a resistor, a capacitor, etc. and characteristics of a transistor) of the internal elements becomes apparent only after the integrated circuit chip has been manufactured. Therefore, the variation in them has a large influence upon a clock timing, and such a new technique as the present invention described later is indispensable in case of requiring accurate element parameter values in order to utilize characteristics of the elements to their limits.
In a case that a digital system is an ordinary hardware design data library or a hardware design data library which is considered as an object of intellectual property rights, called IP, and is intended to be used by a third party, its functions and interface requirements are publicly disclosed, but more detailed information than an equivalent circuit related to its internal structure may not be publicly disclosed.
In a case of using such IP in an integrated circuit having a high clock frequency, an accurate timing adjustment reaching the interior being treated as an object of the IP is indispensable. However, since the interior is often a black box due to IP rights as described above, in order to manufacture an integrated circuit operating at a high clock frequency while keeping such rights, it is necessary to provide a clock circuit to generate data of the optimum input and output timing for each IP at an external circuit side. However, since even if the same IP is used, the optimum input/output timing varies in each chip, the prior technique has been unable to manufacture such an integrated circuit.
Additionally, most of the present digital systems use a CMOS technology and in case that a digital system is formed using a CMOS technology, most of a power source current flows when each digital signal changes (from logic value “0” to logic value “1” or from logic value “1” to logic value “0”).
If a number of digital signals change at the same time, therefore, a large power source current flows instantaneously and insufficiency of the power capacity makes a power source voltage change and, in its turn, may cause an erroneous operation.
Furthermore, in comparison with a case where a small current flows continuously, when a large current flows instantaneously, the power consumption is made larger and a larger-capacity power source and power feeding lines need to be prepared and these result in making a digital system larger in size.
To decrease an influence of the simultaneous change of digital signals can be attained by finely adjusting the respective signals in timing, namely, the respective flip-flops in timing within a range where the whole system operates correctly, but a conventional technique has been unable to perform such an accurate timing adjustment in consideration of operation of the whole system.
Additionally, an unwanted electromagnetic emission (EMI) generated from a digital system, which has such an influence as making another digital system around it erroneously operate, should be suppressed. This problem is particularly serious in case that a digital system is packaged as a circuit board, and is regulated by various laws of various countries. The EMI is generated when a digital signal changes (from logic value “0” to logic value “1” or from logic value “1” to logic value “0”), and an EMI having a large peak power is generated when a number of digital signals change all at once.
As one way for suppressing this, there is a method of reducing the number of digital signals changing at the same time, namely, the number of flip-flops changing at the same time, but it has been impossible to accurately adjust in timing the flip-flops of the whole digital system within a range where the whole digital system correctly operates at a specified clock frequency by means of a conventional technique.